Fabrication of semiconductor integrated circuits (ICs) is an extremely complex process that involves hundreds of operations. Accordingly, it goes without saying that the hundreds of operations typically required to manufacture such semiconductor ICs create reliability issues. Therefore, in an attempt to increase the yield and reliability of semiconductor ICs, and thereby decrease the cost of the individual chips to the ultimate customer, the IC industry commonly performs tests to recognize and pinpoint various defects that may be affecting the yield of the semiconductor ICs.
Turning to Prior Art FIG. 1, illustrated is a conventional integrated circuit testing device 100 that might be used to perform yield tests. The conventional integrated circuit testing device 100 illustrated in FIG. 1 includes a circuit layer 120 formed on a silicon test chip 110. As is common in the industry, the circuit layer 120 is designed to test a single type of feature (i.e., a collection of similar features such as a collection of source/drain regions, a collection of wells, a collection of gate oxides, a collection of gate electrodes, a collection of interconnects, etc.) using three different test device areas. In the particular example of FIG. 1, the integrated circuit testing device 100 includes first, second and third test devices 130, 134, 138, having first, second and third areas, respectively, scaling in a desired fashion. As is known to those skilled in the art, the differing areas allow a defect density as well as a systematic yield loss to be calculated. By applying a test signal through the plurality of bond pads 140 located on the silicon test chip 110, yield measurements may be obtained.
Typically each conventional integrated circuit testing device 100 is limited to 20 bond pads. Generally, this is a result of pre-configured and conventional probe cards being used. Therefore, the bond pads for the conventional integrated circuit testing device 100 are typically fixed within a technology development and through a production cycle, and do not have much freedom of change due to cost and test standard implementation reasons. Accordingly, the limited number of bond pads substantially limits the number of features that can be tested using a single integrated circuit testing device 100. For example, because each of the test devices 130, 134, 138 require up to six independent pre-configured and hard wired bond pads (total of 18 bond pads) the integrated circuit testing device 100 is prevented from testing more than a single type of feature.
Unfortunately, each type of feature in a proposed IC layout process (e.g., typically consisting of about one hundred independent features for the entire process) must be tested, and therefore, each type of feature requires its own individual integrated circuit testing device 100. The prior art accommodates this requirement by forming multiple integrated circuit testing devices 100 adjacent one another on the silicon test chip 110. Typically, each of the multiple integrated circuit testing devices 100 must have a comparable equivalent area to the real product integrated circuit to get meaningful defect density data. Consequently, the multiple integrated circuit testing devices 100 use a substantial amount of silicon test chip 110 area. For example, for a typical analog CMOS process, about one hundred integrated circuit testing devices 100 are needed to conduct the minimum design rule test and one sub-design-rule test. These one hundred integrated circuit testing devices 100 typically occupy from about 40% to about 60% of the silicon test chip 110 area. As those skilled in the art are quite aware, the expense associated with this silicon test chip 110 area is proportional to the silicon occupied, and therefore costly.
Accordingly, what is needed in the art is an integrated circuit testing device that does not experience the drawbacks, especially the large amount of required silicon area, experienced by the prior art structures.